BACKGROUND OF THE INVENTION 1. Field of the Invention
This invention relates to a shared contact used in a semiconductor device and a manufacturing process therefor.
2. Description of the Prior Art
An SRAM (Static Random Access Memory) is widely used as a cache memory for a computer or a system memory for a terminal. The SRAM is composed of a flip-flop circuit where each cell stores one bit. The SRAM requires at least four transistors, so that it has been integrated at a quarter of a pace for a DRAM (Dynamic Random Access Memory).
FIG. 5 shows a plan view of a conventional loadless type of SRAM, and FIG. 6 shows its equivalent circuit. FIGS. 5 and 6 are based on K. Noda et al., A 1.9-xcexcm2 Loadless CMOS Four-Transistor SRAM Cell in a 0.18-xcexcm Logic Technology, IEDM98, pp.643-646, 1998.
There will be described the equivalent circuit of FIG. 6. The four-transistor type of loadless SRAM cell consists of two access transistors constituted by a p-type MOSFET (101, 102) and two driver transistors constituted by an n-type MOSFET (103, 104). Each gate (105, 108) in the access transistors (101, 102) is connected to a word line (117), while each source (106, 110) in the access transistor (101, 102) is connected to a bit line (118, 119). Sources (113, 116) in the driver transistors (103, 104) are grounded, while a gate (111, 114) in one driver transistor (103, 104) is connected to a drain (115, 112) in the other driver transistor. For connection of the access transistor to the driver transistor, the drain (107) in the access transistor (101) is connected to the drain (112) in the driver transistor (103) and the gate (114) in the driver transistor (104) at the point 120, while the drain (109) in the access transistor (102) is connected to the drain (115) in the driver transistor (104) and the gate (111) in the driver transistor (103) at the point 121.
The connection points 120 and 121 in FIG. 6 are of a unique connection style employed in an SRAM. A shared contact is used to utilize them as a device element on a substrate.
There will be described a plan view in FIG. 5 for a conventional loadless type of SRAM cell prepared in accordance with the prior art. In the figure, 201 is an access transistor constituted by a p-type MOSFET which consists of a gate electrode (205), a source region (206) and a drain region (207), and 202 is also an access transistor constituted by a p-type MOSFET which consists of a gate electrode (205), a source region (210) and a drain region (209). The gate electrode (205) in the access transistor (201, 202) is a word line. Next, 203 is a driver transistor constituted by an n-type MOSFET which consists of a gate electrode (211), a source region (213) and a drain region (212), and 204 is also a driver transistor consisting of a gate electrode (214), a source region (216) and a drain region (215).
The drain region (207) in the access transistor (201) is connected to the gate electrode (214) in the driver transistor (204) via a shared contact (228) which corresponds to connection of 109 with 111 at 121 in FIG. 6, and to the drain region (212) in the driver transistor (203) via a shared contact (225) which corresponds to connection of 115 with 111 at 121 in FIG. 6.
The drain region (209) in the access transistor (202) is connected to the gate electrode (211) in the driver transistor (203) via a shared contact (227) which corresponds to connection of 107 with 114 at 120 in FIG. 6, and to the drain region (215) in the driver transistor (204) via a shared contact (226) which corresponds to connection of 112 with 114 at 120 in FIG. 6.
Furthermore, a contact is, but not shown, formed on the source region (206, 210) in the access transistor (201, 202) and connected to a bit line formed on an upper layer, while a contact is, but also not shown, formed on the source region (213, 216) in the driver transistor (203, 204) and connected to a grounding line formed on an upper layer.
The cell in FIG. 5 is surrounded by other cells. In FIG. 5, cells are vertically aligned, in which devices are disposed as a mirror image. Horizontally, there are also aligned cells in which devices are disposed as a mirror image. For example, the source region (216) in the driver transistor (204) is shared with the left adjacent cell as its source region.
It is also true for the right adjacent cell.
As described above, SRAM cells are aligned such that a common source region is shared by their driver transistors.
An illustrative process for manufacturing an SRAM cell according to the prior art will be described with reference to cross sections (FIGS. 7(a) to (c)) taken on the line X-Xxe2x80x2 in the plan view of FIG. 5.
As shown in FIG. 7(a), on a silicon substrate are formed a isolation region (not shown) and a p-type well region (not shown) by a known process, and then a gate oxide film (301) and gate electrodes (302, 303). The p-type well region can be formed, for example, by implanting B+ at an ion-implantation energy of 300 keV, a dose of 2xc3x971013 atoms/cm2 and an implantation angle of 0xc2x0, then at an ion-implantation energy of 150 keV, a dose of 4xc3x971012 atoms/cm2 and an implantation angle of 0xc2x0 and finally at an ion-implantation energy of 30 keV, a dose of 8xc3x971012 atoms/cm2 and an implantation angle of 0xc2x0.
A gate oxide film (301) is formed to about 4 nm, for example, by thermal oxidation; for example, a polycrystal silicon film with a thickness of about 160 nm is deposited on the whole surface of a substrate. Then, it is subject to photolithography and dry etching to provide a gate electrode with a desired shape. Then, an. n-type dopant (304), e.g., As +, is implanted, for example, at an ion-implantation energy of 10 keV, a dose of 1xc3x971014 atoms/cm2 and an implantation angle of 0xc2x0 to form an n-type LDD region (305).
Then, as shown in FIG. 7(b), side walls (306, 307) consisting of a silicon oxide film are formed to a width of 100 nm. They can be readily formed, for example, by depositing a silicon oxide film on the whole surface of a substrate to a thickness of about 120 nm by LPCVD and then etching back the whole surface of the substrate by RIE (Reactive Ion Etching). Then, an n-type dopant (308), e.g., As+, is implanted, for example, at an ion-implantation energy of 45 kev, a dose of 5xc3x971015 atoms/cm2 and an implantation angle of 0xc2x0 to form an n+type source-drain region (309). Then, silicide layers (310, 311) are formed on the gate electrodes (302, 303) and the source-drain region (309) by a known procedure.
Then, as shown in FIG. 7(c), an interlayer insulating film (312) made of a silicon nitride film, a silicon oxide film or the like is formed, and the area to be a shared contact is removed by etching and then filled with, e.g., tungsten by a known procedure to form a shared contact (313).
An SRAM cell according to the conventional technique (FIGS. 7(a) to 7(c)), however, has the following drawbacks.
a) The shared contact for the conventional SRAM cell is extended over the side wall (306) like a bridge to be connected with the gate electrode (302) and the source-drain region (309), and consequently protrude toward the adjacent gate electrode (303).
b) The contact area of the shared contact cannot be reduced for further ensuring an adequate conductivity.
In conclusion, according to the process of the prior art, it is required to form the shared contact protruding from the gate electrode (302) toward the adjacent gate electrode (303) to about 180 nm which is the sum of the width, 100 nm, of the side wall (306) and the contact width, 80 nm, of the contact electrode with the source-drain region.
Since the adjacent gate electrode (303) has a side wall (307) with a width of 100 nm, a distance between gate electrodes must be 280 nm in total. The distance between gate electrodes cannot be, therefore, reduced to less than the dimension, 280 nm, and thus the cell size cannot be reduced.
In the light of the above problems, an objective of this invention is to provide a process for manufacturing a shared contact without protrusion toward an adjacent gate electrode and an improved shared contact.
This invention provides a process for manufacturing a shared contact in a semiconductor device with a flip-flop circuit or a semiconductor device where a gate electrode in one MOSFET is electrically connected to a source or drain region in another MOSFET, essentially consisting of the steps of:
1) forming a gate electrode in a desired shape on a semiconductor substrate surface;
2) depositing an insulating material on the whole surface of the semiconductor substrate and etching it back to form a side wall made of the insulating material on the side of the gate electrode;
3) etching the substrate using a resist having an opening to a predetermined area of the gate electrode surface as a mask to remove the gate electrode in the predetermined area for exposing the substrate surface;
4) removing the resist and ion-implanting a dopant whose conduction type is different from that in the semiconductor substrate, to the exposed semiconductor substrate in the area where the gate electrode has been removed and to the source-drain region;
5) depositing an interlayer insulating film on the whole surface of the substrate and removing the interlayer insulating film in the area where the gate electrode has been removed to form a contact hole; and
6) filling a conductive material in the contact hole.
This invention also provides a shared contact used in a semiconductor device with a flip-flop circuit or a semiconductor device where a gate electrode in one MOSFET is electrically connected to a source or drain region in another MOSFET, characterized in that the bottom surface of the shared contact is in contact with a dopant diffusion layer formed on the surface of the semiconductor surface , the side surfaces of the shared contact are in contact with cross sections of the gate electrode , and the substrate surface is electrically connected with the cross section of the gate electrode.